Field of the Invention
The present invention relates to a semiconductor storage device including a memory cell array formed by arraying a plurality of memory cells each comprising a variable resistor element for storing information through change in electrical resistance in a row direction and a column direction, more specifically, to a technique of preventing and suppressing degradation of stored data involved in read operation of the memory cell array.
In recent years, as a next-generation Nonvolatile Random Access Memory (NVRAM) capable of being operated at a high speed in place of a flash memory, various device structures such as a Ferroelectric RAM (FeRAM), a Magnetic RAM (MRAM, and an Ovonic Unified Memory (OUM) or the like are proposed and in view of a high performance, a high reliability, a low cost, and a process matching, competition in development of them has been intensified. However, these current memory devices have both merits and demerits respectively and it is difficult to realize the ideal “universal memory” having each merit of a SRAM, a DRAM, and the flash memory.
On the contrary to these existing arts, a method of changing an electric resistance in a reversible fashion by applying a voltage pulse to a perovskite material that is known as a supergiant magnetic resistance effect is disclosed by Shangquing Liu and Alex Ignatiev et al. of University of Houston (refer to the specification of U.S. Pat. No. 6,204,139, Patent Application No.2002-8369, Liu, S. Q. et al., “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol., 76, pp. 2749-2751, 2000). This is very epoch-making because the resistance change across several digits appears even at room temperature without applying a magnetic field while using the perovskite material that is known as the supergiant magnetic resistance effect. A Resistive Random Access Memory (RRAM) does not require any magnetic field differently from the MRAM, so that this has an excellent advantage such that the power consumption is very low, minuteness and high integration can be easily realized, and multilevel storage is possible since a dynamic range of the resistance change is very large as compared to the MRAM. The basic structure of the real device is very simple, and it is made in such a manner that a lower electrode material, the perovskite-type metal oxide, and an upper electrode material are deposited in a direction vertical to a substrate. In the meantime, according to the element structure illustrated in the specification of U.S. Pat. No. 6,204,139, the lower electrode material is made of a yttrium barium copper oxide YBa2Cu3O7 (YBCO) film deposited on a single crystal substrate of a lantern—aluminum oxide LaAlO3 (LA); the perovskite-type metal oxide is made of a crystalline praseodymium calcium manganic oxide Pr1−xCaxMnO3 (PCMO) film; and the upper electrode material is made of an Ag film deposited by sputtering, respectively. It is informed that the operation of this memory element can change the resistance in the reversible fashion by applying 51 volt of the voltage pulse between the upper and lower electrodes in positive and in negative. It means that a new nonvolatile memory device is available by reading a resistance value in this reversible resistance change operation (hereinafter, referred to as “the switching operation” appropriately).
The nonvolatile semiconductor memory device is configured by forming a memory cell array by arraying a plurality of memory cells each comprising a variable resistor element configured with PCMO film and the like for storing information through change in electrical resistance of the variable resistor element in the row direction and the column direction, and arranging a circuit for controlling write, erase, and read of data with respect to each memory cell of the memory cell array on the periphery of the memory cell array.
The configuration of the memory cell comprising the variable resistor element includes a case of configuring each memory cell with a series circuit in which the variable resistor element and a selective transistor are connected in series and a case of configuring each memory cell only with the variable resistor element. The memory cell of the former configuration is referred to as a 1T/1R type memory cell, and the memory cell of the latter configuration is referred to as a 1R type memory cell.
A configuration example of configuring a large-capacity nonvolatile semiconductor memory device by forming the memory cell array with 1T/1R type memory cells will now be described using the diagrams.
FIG. 1 is a view showing a frame format of one configuration example of the memory cell array of 1T/1R type memory cell, and a similar memory cell array configuration is disclosed in Patent application (Patent Application No. 2003-168223) filed by the present applicant. In this memory cell array configuration, the memory cell array 1 has a configuration in which m×n number of memory cells 2 are each arranged at an intersection of m number of bit lines (BL1 to BLm) extending in the column direction and n number of word lines (WL1 to WLn) extending in the row direction. Further, n number of source lines (SL1 to SLn) is arranged parallel to the word line. In each memory cell, the upper electrode of the variable resistor element 3 is connected to the drain electrode of the selective transistor 4, the lower electrode of the variable resistor element 3 is connected to the bit line, the gate electrode of the selective transistor 4 is connected to the word line, and the source electrode of the selective transistor 4 is connected to the source line. It is to be noted that the relationship between the upper electrode and the lower electrode of the variable resistor element 3 may be inverted, or the lower electrode of the variable resistor element 3 may be connected to the drain electrode of the selective transistor 4, and the upper electrode of the variable resistor element 3 may be connected to the bit line.
Therefore, by configuring the memory cell 2 with the series circuit of selective transistor 4 and variable resistor element 3, the selective transistor 4 of the memory cell 2 selected by the potential of the word line is turned on, and further, the write or erase voltage is selectively applied only to the variable resistor element 3 of the memory cell 2 selected by the potential of the bit line thereby allowing the resistance value of the variable resistor element 3 to be changed.
FIG. 2 shows one configuration example of the nonvolatile semiconductor memory device comprising the memory cell array 1 of 1T/1R type memory cell. A specific memory cell in the memory cell array 1 corresponding to an address input, which is input from the address line 8 to a control circuit 10, is selected by a bit line decoder 5, a source line decoder 6, and a word line decoder 7, each operation of write, erase, and read of data is carried out, and thus the data is stored into and read out from the selected memory cell. The input/output of data with an external device (not shown) is performed via the data line 9.
The word line decoder 7 selects the word line of the memory cell array 1 corresponding to the signal input to the address line 8, the bit line decoder 5 selects the bit line of the memory cell array 1 corresponding to the address signal input to the address line 8, and the source line decoder 6 selects the source line of the memory cell array 1 corresponding to the address signal input to the address line 8. The control circuit 10 performs control in each operation of write, erase, and read of the memory cell array 1. The control circuit 10 controls the word line decoder 7, the bit line decoder 5, the source line decoder 6, a voltage switch circuit 12, and read, write, and erase operations of the memory cell array 1 based on the address signal input from the address line 8, a data input (during write) input from the data line 9, and a control input signal input from a control signal line 11. In the example shown in FIG. 2, the control circuit 10 has functions serving as, although not shown, a general address buffer circuit, a data input/output buffer circuit, and a control input buffer circuit.
The voltage switch circuit 12 switches and provides to the memory cell array 1, each voltage of the word line, the bit line, and the source line necessary for read, write, and erase of the memory cell array 1 in accordance with the operation mode. It is to be noted that Vcc is the power supply voltage of the nonvolatile semiconductor memory device, Vss is the ground voltage, Vpp is the write or erase voltage, and V1 is the read voltage. The data is read from the memory cell array 1 by way of the bit line decoder 5 and the read circuit 13. The read circuit 13 determines the state of the data, and transfers the result thereof to the control circuit 10, which then outputs the same to the data line 9.
A configuration example of a large-capacity nonvolatile semiconductor memory device by forming the memory cell array with the 1R type memory cell will now be explained using the diagrams. As shown in FIG. 3, the memory cell 14 is not configured with the series circuit of selective transistor and variable resistor element but is configured only with the variable resistor element 3. The 1R type memory cell 14 is arrayed in a matrix form to configure the memory cell array 15, similar to that disclosed in the Patent article 2 and the like. More specifically, the memory cell array 15 has a configuration in which m×n number of memory cells 14 are each arranged at the intersection of m number of bit lines (BL1 to BLm) extending in the column direction and n number of word lines (WL1 to WLn) extending in the row direction. In each memory cell 14, the upper electrode of the variable resistor element 3 is connected to the word line, and the lower electrode of the variable resistor element 3 is connected to the bit line. It is to be noted that the relationship between the upper electrode and the lower electrode of the variable resistor element 3 may be inverted, or the lower electrode of the variable resistor element 3 may be connected to the word line and the upper electrode of the variable resistor element 3 may be connected to the bit line.
In the memory cell array 1 (refer to FIG. 1 and FIG. 2) configured with the 1T/1R type memory cell 2, when selecting the memory cell to read, write, erase the data, a predetermined bias voltage is applied to the selected word line and the selected bit line thereby turning on only the selective transistor included in the selected memory cell connected to both the selected word line and the selected bit line. The read current thus flows only to the variable resistor element included in the selected memory cell. On the other hand, in the memory cell array 15 configured with the 1R type memory cell 14, when selecting the memory cell to read the data, a similar bias voltage is also applied to the selected memory cells connected to the word line and the bit line in common with the memory cell to be read. The read current thus also flows to the memory cells other than the memory cell to be read. The read current that flows through the selected memory cells selected in row units or column units is detected as the read current of the memory cell to be read by column selection or row selection. In the memory cell array 15 configured with the 1R type memory cell 14, the read current also flows to the memory cells other than the memory cell to be read, but has advantages in that the memory cell structure is simple and that the memory cell area, and further, the memory cell array area are small.
FIG. 3 and FIG. 4 show a conventional example of the procedures for applying voltage to each part during read operation of the data in the memory cell array 15 configured with the 1R type memory cell 14. When reading the data of the selected memory cell, the selected word line connected to the selected memory cell is maintained at ground potential Vss, and during the read period Tr, the read voltage V1 is applied to all the other non-selected word lines and all the bit lines. As voltage difference of read voltage V1 is created between the selected word line and all the bit lines during the read period Tr, the electrical resistance, that is, the read current corresponding to the storage state flows to the variable resistor element of the selected memory cell thereby allowing the data stored in the selected memory cell to be read. In this case, the read current corresponding to the storage state of the selected memory cell connected to the selected word line flows to each bit line, and thus data of the specific selected memory cell is read by selectively reading the read current flowing through a predetermined selected bit line on the bit line side. It is to be noted that the relationship between the bit line and the word line may be interchanged, in which case the read current flowing through each word line is selectively read on the word line side.
FIG. 5 shows one configuration example of the non-volatile semiconductor memory device comprising the memory cell array 15 of 1R type memory cell 14. A specific memory cell in the memory cell array 15 corresponding to the address input, which is input from the address line 18 to the control circuit 20, is selected by the bit line decoder 16 and the word line decoder 17, each operation of write, erase, read of the data is carried out, and thus the data is stored into and read out from the selected memory cell. The input/output of data with the external device (not shown) is performed via the data line 19.
The word line decoder 17 selects the word line of the memory cell array 15 corresponding to the signal input to the address line 18, and the bit line decoder 16 selects the bit line of the memory cell array 15 corresponding to the address signal input to the address line 18. The control circuit 20 performs control in each operation of write, erase, and read of the memory cell array 15. The control circuit 20 controls the word line decoder 17, the bit line decoder 16, the voltage switch circuit 22, and the read, write and erase operations of the memory cell array 15 based on the address signal input from the address line 18, the data input (during write) input from the data line 19, and the control input signal input from the control signal line 21. In the example shown in FIG. 5, the control circuit 20 has functions serving as, although not shown, a general address buffer circuit, a data input/output buffer circuit, and a control input buffer circuit.
The voltage switch circuit 22 switches and provides to the memory cell array 15, each voltage of the word line, the bit line, and the source line necessary for read, write, and erase of the memory cell array 15 in accordance with the operation mode. It is to be noted that Vcc is the power supply voltage of the nonvolatile semiconductor memory device, Vss is the ground voltage, Vpp is the write or erase voltage, and V1 is the read voltage. The data is read from the memory cell array 15 by way of the bit line decoder 16 and the read circuit 23. The read circuit 23 determines the state of the data, and transfers the result thereof to the control circuit 20, which then outputs the same to the data line 19.
The variable resistor element configuring the 1T/1R type memory cell and the 1R type memory cell includes, for example, a phase change memory element that changes the resistance value depending on the crystal of chalcogenide/change of state of amorphous, an MRAM element that uses the resistance change by the tunnel magneto-resistance effect, a memory element of polymer ferroelectric RAM (FRAM) in which the resistance element is formed by electrically conductive polymer, and a RAM element that causes resistance change by electrical pulse application.
When reading the data from the memory cell comprising the variable resistor element, the bias voltage is applied to the variable resistor element to flow the read current, the resistance value of the variable resistor element is determined by the amount of the current and then the data is read. Therefore, irrespective of the configuration of the memory cell, the read operation involves application of a predetermined bias voltage to the variable resistor element.
The inventors of the present invention has found that the resistance value of the variable resistor element changes if the read voltage which absolute value is less than or equal to the write voltage is applied to the variable resistor element as a continuous pulse of the same polarity when using the PCMO film (Pr1−xCaxMnO3), one type of perovskite-type metal oxide, as the variable resistor element. As shown in FIG. 6, when the voltage pulse (pulse width of 100 ns) of positive polarity is continued to be applied to the upper electrode of the variable resistor element, the resistance value of the variable resistor element, which initial state is in a high resistance state, lowers as the number of pulse applications is increased (open triangle in FIG.6) Further, when the voltage pulse (pulse width of 100 ns) of negative polarity is continued to be applied, the resistance value increases as the number of pulse applications increases (filled triangle in FIG.6).
The voltage pulse of positive polarity refers to the state in which the ground voltage acting as the reference is provided to the lower electrode, and the positive voltage pulse (e.g., 1V) is applied to the upper electrode. Further, the voltage pulse of negative polarity refers to the state in which the ground voltage acting as the reference is provided to the upper electrode, and the positive voltage pulse (e.g., 1V) is applied to the lower electrode. The measurement conditions of the resistance value shown in FIG. 6 are derived from the current value of when the ground voltage acting as the reference is provided to the lower electrode, and 0.5V is applied to the upper electrode. The axis of abscissa of FIG. 6 shows the logarithmic representation of the relative application number of the voltage pulse.
Open circles in FIG. 7 shows the result of research on resistance change of when the positive voltage pulse is applied to the upper electrode of the variable resistor element, which initial state is in the low resistance state. Filled circles in FIG. 7 show resistance change when the negative voltage pulse is applied and open squares show an example of resistance change when the voltage pulses of positive polarity and negative polarity are alternately applied. It is to be noted that the measurement conditions of the resistance value shown in FIG. 7 are derived from the current value of when the ground voltage acting as the reference is provided to the lower electrode, and 0.5V is applied to the upper electrode. The axis of abscissa of FIG. 7 is the logarithmic representation of the relative application number of the voltage pulse. It is apparent from FIG. 7 that the resistance change is small compared to when the initial state is in the high resistance state. In particular, the voltage applied to the variable resistor element during read is usually desired to be about 1V, but the resistance change is small at 1V or −1V.
Therefore, from the above experiment results, a read disturb phenomenon in which the data stored in the memory cell, that is, the resistance value changes in accordance with the number of voltage pulse applied with the read operation is recognized. In particular, when the read operation is performed by applying the voltage pulse of positive polarity to the variable resistor element, which resistance state during read is high resistance state, the resistance value of the relevant variable resistor element lowers, the resistance difference between the high resistance state and the low resistance state becomes small, and the read margin lowers. Further, when the read operation is repeated on the same memory cell, in the worst case, the stored data may be completely lost and the read operation may become impossible to be performed any further.
Moreover, in the memory cell array formed with the 1R type memory cell, the read voltage is applied also to the memory cells other than the selected memory to be read having the word line or the bit line in common with the memory cell to be read, and thus the read disturb phenomenon is more significantly recognized.